1. Field of the Invention
This invention relates to microprocessor compilers. In particular, the invention relates to binary translation.
2. Description of Related Art
Binary translation is a process to translate a source binary code for a source architecture into a translated code to be run on a target architecture. Typically, the target architecture is different than the source architecture. The differences may include instruction set architecture (ISA), number of registers, and register format. Among these, the difference in register format presents many difficulties for binary translation. The problem becomes complicated when the source architecture has multiple register formats and the target architecture cannot support all of these formats in a single register. For example, the source architecture may support three different formats: packed single precision floating-point (PS), packed double precision floating-point (DS), and packed integer (PINT). A register having 128 bits may contain four 32-bit data in PS format, two 64-bit data in DS format, or one 128-bit data in PINT format. The source architecture has instructions designed to operate on these registers with different content format but the target architecture may not support all three formats in a single register.
Existing techniques to solve this format incompatibility problem include inserting extra code to detect the format difference and to perform format conversion. The extra code incurs overhead to the binary translation. This overhead results in large code size and degraded performance. This is especially more significant when the number of registers in the block of code to be translated is large.
Therefore, there is a need to have an efficient technique to maintain compatibility on register format in binary translation.